In a semiconductor device having DRAM or the like, high degree of integration is attained by the reduction of a memory cell area. This means that the area occupied by a capacitor portion is inevitably decreased. With all that, for preventing soft errors, a predetermined quantity of stored charges required for reading of a memory has to be ensured. That is, for higher integration of a semiconductor device, it is for a means that increases the quantity of stored charges for unit area.
One of the means described above can include application of an oxide dielectric material with high relative dielectric constant to a capacitor insulating film. At present, silicon oxide films (SiO2 film, relative dielectric constant: 3.8) and silicon nitride films (Si3N4 film, relative dielectric constant: 7–8) have been used as the capacitor dielectric film at present. Instead of them, it has now been studied on the use of tantalum pentoxide films (Ta2O5 film, relative dielectric constant: 20–25) or oxide dielectric materials having a relative dielectric constant of 100 or more, for example, strontium titanate [SrTiO3(STO)], barium strontium titanate [(Ba, Sr)TiO3{BST}], lead titanate zirconate [Pb(Zr, Ti)O3{PZT}] and bismuth type layerous ferroelectric materials. Among them, PZT or bismuth type layerous ferroelectric material is applicable also to ferroelectric memories utilizing the ferroelectric property thereof. However, in a memory of a Gbit scale, quantity of stored charges required for reading is insufficient even when an oxide dielectric material of high relative dielectric constant is adopted as the capacitor dielectric film. Accordingly, it is necessary to make the capacitor portion into a three-dimensional form to substantially increase the capacitor area.
The oxide dielectric material requires film formation or post-annealing at a high temperature of at least 400° C. to 700° C. and in an oxidizing atmosphere for improving the electrical characteristics thereof. In this case, when a lower electrode is oxidized by oxygen in the atmosphere, a dielectric film of lower dielectric constant than a capacitor dielectric film is formed to result in substantial decrease in the capacitance of the capacitor. Further, when a barrier layer or a plug situating below the lower electrode is oxidized, electrical conductivity between a transistor and a capacitor is lost. Then, platinum (Pt) which is relatively stable to an atmosphere at high temperature and to oxidizing atmosphere, or ruthenium (Ru) or iridium (Ir) keeping conductivity even when the oxide is formed has been studied as an effective candidate for the lower electrode. Among them, ruthenium which is particularly excellent in fine fabricability is a most preferred material as a lower electrode of an oxide dielectric material. Further, since the electric characteristic of a capacitor depends on the dielectric material/electrode interface characteristic, it is necessary to use the same material as the lower electrode for the upper electrode.
In summary, in a memory of a Gbit scale, since the area that capacitor can occupy is small, the quantity of stored charges required for reading is possibly insufficient even when an oxide dielectric material of high relative dielectric constant is used. In view of the above, it is necessary to make the capacitor into a three-dimensional form in order to increase substantial capacitor area. Specifically, it requires steps of depositing the lower electrode described above on a structure which has been previously fabricated into a three-dimensional structure and then forming an oxide dielectric material and an upper electrode.
As a method of forming the lower electrode of the three-dimensional structure described above, the formation method by the prior art is to be explained with reference to the drawings and, further, problems or subjects are pointed out.
A method of fabricating a deep hole from the surface of a silicon oxide film which is ease for fine fabrication, then depositing a lower ruthenium electrode by a sputtering method thereby forming a three-dimensional structure is to be described with reference to FIG. 9. All the drawings represent cross sections.
At first, on plugs 1 comprising, for example, titanium nitride and a plug portion interlayer insulating film 2 comprising, for example, a silicon oxide film, is deposited a capacitor portion interlayer insulating film 3 of 700 nm thickness comprising, for example, a silicon oxide film. Then, the capacitor portion interlayer insulating film 3 is fabricated to the surface of the plug portion interlayer insulating film 2 such that an opening has a circular cylindrical shape, elliptic cylindrical shape, or a rectangular shape by using a well-known photolithographic method and a dry etching method. Assuming the width of the deep hole as 130 nm, the aspect ratio of the deep hole (height/width) is 700 nm/130 nm, that is, about 5.4. After forming the deep hole, a lower ruthenium electrode is deposited. In this step, when existent sputtering of poor step coverage is used, no ruthenium film is deposited on the side wall of the deep hole. Therefore, it is necessary to use a formation method of excellent step coverage. This subject can be solved by using a method of sputtering with low pressure and substrate to target distances (long-throw) although the details are to be described later. Then, the lower ruthenium electrode 4 is deposited by the low-pressure and long-throw sputtering [FIG. 9(a)].
In this case, for depositing ruthenium to 20 nm thickness on the side wall of the opening, it is necessary to deposit ruthenium of about 300 nm to the upper surface. Since sputtering particles have high straight forwarding property, the thickness of ruthenium deposited at the bottom of the deep hole is 40 nm which is about twice the thickness on the side wall.
Then, for separating adjacent capacitors electrically, when the lower electrode deposited on the upper surface of the capacitor portion interlayer insulating film 3 is removed by sputter etching, a lower electrode having a three-dimensional structure can be formed [FIG. 9(b)].
Subsequently, an oxide dielectric film 5 comprising, for example, tantalum pentoxide of about 10 nm thickness is deposited by chemical vapor deposition [FIG. 9(c)].
Then, the height of the deep hole is decreased by so much as the thickness of the ruthenium at the bottom (40 nm) and the thickness of the dielectric material (10 nm) into about 650 nm. On the other hand, the width of the deep hole is decreased by so much as twice of the ruthenium film thickness on the side wall (20 nm) and twice of the dielectric film thickness (10 nm) into about 70 nm. Accordingly, the aspect ratio is 70 nm/650 nm, that is, about 9.3 upon forming the upper electrode and it increases to about 1.7 times when the lower electrode is formed. Therefore, even when the upper electrode 30 comprising, for example, ruthenium is deposited by the low-pressure and long-throw sputtering, it causes an additional subject that the ruthenium film is deposited on the side wall of the deep hole [FIG. 9(d)].
In summary, in the step of manufacturing a concave shape capacitor, no lower ruthenium electrode can be formed by the existent sputtering method. In addition, the aspect ratio increases further upon forming the upper electrode. Therefore, it has been demanded for a method of forming a ruthenium electrode of high coverage.